1. Field of the Invention
The present invention relates to a semiconductor device including memory cell region which has a composite gate structure consisting of a floating gate and a control gate and to a method of manufacturing the same.
2. Description of the Related Art
Along with recent multifunctioning of various portable electronic devices or home appliances, a technique of integrating, in a logic LSI represented by one-tip-microcomputer, a nonvolatile semiconductor memory which has an electric charge accumulation layer to hold stored data even after the power-OFF is becoming more important. The nonvolatile semiconductor memory uses, as the electric charge accumulation layer, a floating gate, a two-layer film (NO film) constituted by a nitride film and an oxide film, a three-layer film (ONO film) constituted by an oxide film, a nitride film and an oxide film, or the like. The nonvolatile semiconductor memory having a floating gate is represented by an EEPROM. The nonvolatile semiconductor memory having an NO film is called an MNOS transistor and the memory having an ONO film is called an MONOS transistor.
The nonvolatile semiconductor memory is developing into a multivalued memory which stores one of predetermined multivalued data of ternary or more. One instance of a multivalued EEPROM or MNOS transistor is disclosed in Japanese Patent Laid-Open No. 8-235886.
Generally, the memory cell structure of an EEPROM or the like has a floating gate and a control gate (word line), and a bit line is formed on this control gate with an insulating interlayer intervened therebetween.
However, with recent progress in micropatterning and integration of semiconductor devices, a contact hole formed to connect a bit line and a drain diffusion layer is required to be smaller in diameter. In this case, the aspect ratio of the contact hole becomes high because its diameter becomes small relative to its depth. Therefore, the requirement of position accuracy becomes stricter in formation of the contact hole. To relax this requirement of position accuracy, the aspect ratio of the contact hole must be made as low as possible.
Japanese Patent Laid-Open No. 2-28379 discloses a nonvolatile semiconductor memory in which the word line and the bit line are simultaneously formed using the same material. In this nonvolatile semiconductor memory, the word line and the bit line do not cross each other but are formed in parallel, thus substantially forming a single layer structure. With this structure, the depth of the contact hole formed for bit contact can have a small value, i.e., almost the same value as that of the thickness of a single insulating interlayer formed on the surface of the semiconductor substrate.
However, the nonvolatile semiconductor memory has the following problem. When the word line and the bit line are formed in parallel so as not to cross each other, a plurality of transistors electrically connected to one bit line through corresponding contact holes formed under this bit line are simultaneously selected in the operation of the nonvolatile semiconductor memory. For this reason, the nonvolatile semiconductor memory cannot be normally operated because of its memory cell array structure.
Even if the above problem can be avoided by some means, no decoders can be arranged in the periphery of the memory cell array of the nonvolatile semiconductor memory.